The present invention relates to an image acquisition circuit and a signal processing method which samples and holds image signal from a solid-state image sensor using a plurality of charge-coupled devices, applies gain to the sampling output, and then converts the output to a digital signal.
As shown in FIG. 1, a consumer CCD (charge-coupled device) camera conventionally mounts minimal parts including a CCD 52 on a CCD circuit board 51 placed at the rear of a lens. Generally, such a consumer CCD camera employs the following signal transmission system. A CCD signal (image signal) is buffered in a buffer circuit 53 and is sent to a main circuit board 55 via a flexible wire 54. The signal is then sent to a chip (CCD front end) 57 which integrates a correlated double sampling (called CDS hereafter) circuit 58, a gain control amplifier (called GCA hereafter) 59, and an A/D converter (called ADC hereafter) 60. This signal transmission system is generally used for many camera systems because of a small number of chips, space-saving installation, and cost effectiveness. To maintain high-quality camera images without destroying waveforms, this conventional signal transmission system needs to send a wide-band CCD signal to the CCD front end 57 via the flexible wire 54 between circuit boards. The flexible wire 54 is also used for supplying power and CCD drive pulses.
Conventionally, consumer video cameras use a pixel rate of 18 MHz at the highest. The above-mentioned conventional signal transmission system has been free from serious problems.
According to a recent trend of using high-pixel CCDs, some systems are designed to use a pixel rate of 30 to 40 MHz. A CCD waveform at pixel rate P (Hz) contains two effective data levels (reference and signal levels) per cycle and reset coupling of a CCD""s charge-voltage converter. Accordingly, this waveform should contain fundamental-wave components approximately at 4P (Hz). According to a sampling circuit theory, for example, a transmission bandwidth of 1.1Q (Hz), namely 4.4P (Hz), is required for sampling, a signal of pixel rate Q (Hz) at 10-bit accuracy. The above-mentioned CCD needs a bandwidth of approximately 80 MHz when operating at a rate of 18 MHz. The same CCD requires a bandwidth of approximately 180 MHz when operating at a high-speed rate of 40 MHz. When the conventional system configuration is used for a high-speed CCD signal at 30 to 40 MHz, parasitic inductance and capacitance of the flexible wire greatly affects the high-speed CCD signal. It is very difficult to transmit CCD waveform with sufficient performance. If such parasitic inductance and capacitance of the flexible wire is not decreased, the CDS accuracy is degraded and a high S/N ratio can not easily be achieved.
One possible option to solve this problem is shown in FIG. 2. It installs a CCD front end chip on a CCD circuit board 61 near CCD 62 via a capacitor 63. The CCD front end chip 64 comprises a CDS circuit 65, a GCA circuit 66, and an ADC circuit 67. A main circuit board 70 is supplied with 10-bit digital data from a flexible wire 68. The flexible wire 68 is provided with a line 69 which supplies control signals CNT from the main circuit board 70 to the CCD front end chip 64.
This example can solve the above-mentioned problem of CCD waveform transmission between circuit boards, but causes the following problems.
Provision of the CCD front end 64 inevitably increases a CCD circuit board area. An increased area at the rear end of a lens gives serious effect to a design flexibility of small-size products.
The front end chip 64 also heats up the CCD 62, increasing a fixed-pattern noise, especially a white defective noise.
It is necessary to transfer a control signal to the front end chip 64 or transmit high-speed, large-amplitude digital output data between circuit boards. These factors further make it difficult to design small-size products. Letting digital signals pass a flexible wire easily causes a problem due to unnecessary radiation.
FIG. 3 shows another option. A CCD circuit board 71 is provided with a CCD front end chip 74 which integrates a CDS circuit 75 and a GCA circuit 76. The CCD front end chip 74 is connected to a CCD 72 via a capacitor 73. An ADC circuit 80 is mounted on a main circuit board 79 which is connected to the CCD circuit board 71 via a flexible wire 77. The flexible wire 77 contains a line 78 for supplying control signals CNT from the main circuit board 79 to the CCD front end chip 74.
This system just requires a frequency bandwidth of 7P (Hz). The CCD operating at 40 MHz just requires a bandwidth of 44 MHz in contrast to 180 MHz in the above-mentioned example. This value is even smaller than the bandwidth of transmitting an 18 MHz CCD waveform (80 MHz) between circuit boards.
Generally, a chip integrating the CDS circuit and the GCA circuit is not small enough to install on the CCD circuit board. Among three functions needed for the front end, the GCA circuit most consumes power, causing an unsolved problem of heat radiation.
FIG. 4 shows another solution. A CCD 82 and a CDS circuit 84 are mounted on a CCD circuit board 81. The CCD 82 and the CDS circuit 84 are connected via a capacitor 83. A GCA circuit 89 and an ADC circuit 90 are integrated in a same chip 88 and are mounted on a main circuit board 86. The GCA circuit 89 and the ADC circuit 90 are connected to a flexible wire 85 via a capacitor 87.
The system in FIG. 4 transmits CDS outputs between circuit boards in a single-end fashion. If an interfering noise is picked up during the transmission, this system processes and outputs that noise as is.
It is a general practice to supply the CDS chip with a sufficient supply voltage such as 5V-single and perform black level clamping on a succeeding chip input unit for capacity coupling. For providing low power consumption, however, it is desirable to use a 3 V power supply for the CDS chip.
Final outputs from the camera system must comply with digital video (DV), NTSC, or PAL formats. In this case, the camera system needs to be a multi-clock system. For this purpose, the system needs to well resist a beat which is generated due to interference by clocks of different frequencies.
It is undesirable to increase parts installed near the CCD. Installing many parts near the CCD heats the CCD to increase fixed-pattern noise, or places many restrictions on a physical size. This consideration is not limited to high-speed CCDs. It is a general rule to minimize the number of parts mounted on a CCD circuit board.
The present invention has been made in consideration of the foregoing. It is an object of the present invention to provide an image acquisition circuit and a signal processing method which can easily generate image signals with high precision and S/N ratio.
For solving the above-mentioned problems, the image acquisition circuit according to the present invention comprises a first circuit board, a second circuit board, and a wiring unit. On the first circuit board, a CDS chip is mounted near the above-mentioned solid-state image sensing device. The CDS chip samples and holds an image signal from a solid-state image sensor which uses a plurality of charge-coupled devices. The CDS chip then transmits a sampling signal level component as a two-wire signal using two drivers of the same characteristics. The second circuit board comprises a gain control amplifier and an ADC. The gain control amplifier controls gain applied to the above-mentioned sampled signal using the above-mentioned two-wire signal from the CDS chip. The ADC converts the signal level component from this gain control amplifier to a digital signal. The wiring unit connects the first circuit board and the second circuit board by passing the two-wire signal.
For solving the above-mentioned problems, the image signal processing method according to the present invention comprises a first process and a second process. The first process samples and holds an output signal from the solid-state image sensor which uses a plurality of charge-coupled devices. The first process then transmits the sampled signal as a two-wire signal using two drivers ofthe same characteristics. The second process controls gain applied to the above-mentioned sampled signal using the above-mentioned two-wire signal from the first process. The second process then converts the amplified signal into a digital form.
Specifically, the present invention uses two chips for CDS-GCA-ADC processing which is currently performed on a single chip. The CDS chip is mounted on the CCD circuit board. The GCA-ADC chip is mounted on the main circuit board. This architecture minimizes number of wires between the CCD circuit board and the main board, and decreases signal bandwidth to be transmitted between circuit boards down to approximately one fourth of the prior art. Processing is hardly subject to effects of parasitic elements due to transmission between circuit boards.
The CDS chip uses two-wire output. Two same buffer circuits are used for two-wire drivers. An input circuit of the GCA/ADC chip can cancel interfering noise possibly picked up during transmission between circuit boards.
An input clamp is performed on the CDS chip. DC (direct-current) coupling is used for connection between the CDS chip and the GCA/ADC chip. Accordingly, it is possible to operate both chips at a low supply voltage without any additional clamp circuit.
The present invention enables easily generating images with high precision and S/N ratio on an image acquisition system which operates at a high-speed readout clock of 30 to 40 MHz and uses CCD with an extended number of pixels. The present invention provides an excellent immunity against interference noise. The architecture is therefore suitable for a multi-clock camera system for example, where beat noise between different clocks likely becomes a problem. Since no additional clamp circuit is needed, no additional noise occurs therefrom. Another advantage is a 3 V single supply operation, without the need for a 5 V supply, decreasing power consumption. It is also possible to minimize an increase in a circuit board area.